The present invention relates to a semiconductor integrated circuit. More specifically, the present invention relates to a semiconductor integrated circuit capable of performing a transition scan test.
In recent years, a semiconductor integrated circuit has been operated at a higher speed, and the semiconductor integrated circuit has been integrated more progressively. Along with this trend, it has been required to perform an inspection and an operation evaluation on the semiconductor integrated circuit thus produced in a shorter period of time. An evaluation method of the semiconductor integrated circuit includes a scan test.
FIG. 4 is a block diagram showing a conventional scan circuit 100 for performing the scan test. As shown in FIG. 4, the conventional scan circuit 100 includes scan flip-flop circuits (scan FFs) 103a to 103d substituting flip-flop circuits (D-FFs) in the semiconductor integrated circuit. Each of the scan FFs 103a to 103d includes a scan input terminal SD and a scan output terminal Q. In the conventional scan circuit 100, the scan output terminal Q of one of the scan FFs 103a to 103d disposed at a front stage is connected to the scan input terminal SD of another of the scan FFs 103a to 103d disposed at a later stage, thereby constituting a scan path.
More specifically, as shown in FIG. 4, each of the scan FFs 103a to 103d further includes a data input terminal D, so that a multiplexer MUX is disposed at the data input terminal D. Further, the multiplexer MUX includes the scan input terminal SD, so that data can be directly input to each of the scan FFs 103a to 103d. Further, the multiplexer MUX includes a selection terminal SS (also referred to as a scan enable terminal), so that the data input terminal D in a normal operation and the scan input terminal SD can be switched. It is noted that the scan output terminal Q of each of the scan FFs 103a to 103d collectively becomes a data output terminal in the normal operation.
In the conventional scan circuit 100, the scan FFs 103a to 103d are connected (constituting a scan chain), and the scan enable terminal SS of each of the scan FFs 103a to 103d is controlled, thereby making a shift register operation possible. Accordingly, it is possible to evaluate a sequence circuit as a combination circuit 100.
More specifically, when the data input terminal D of each of the scan FFs 103a to 103d is selected through a scan enable signal, each of the scan FFs 103a to 103d captures a value from the combination circuit 101 (referred to as a capture operation). When the scan input terminal SD of each of the scan FFs 103a to 103d is selected through the scan enable signal, each of the scan FFs 103a to 103d performs a shift operation (referred to as a scan shift operation).
One single semiconductor integrated circuit may have a plurality of blocks operating at clocks having different frequencies. Patent Reference 1 has disclosed a technology for performing a data transfer test between such blocks at an actual speed. In the technology disclosed in Patent Reference 1, a reference clock and a frequency division clock are generated. The frequency division clock is generated through dividing a frequency of the reference clock in half.
Patent Reference 2 has disclosed a scan test for evaluating the semiconductor integrated circuit. In the scan test disclosed in Patent Reference 2, a plurality of clock signals having at least one of a different frequency and a different phase is used.    Patent Reference 1: Japanese Patent Publication No. 2009-36668    Patent Reference 2: Japanese Patent Publication No. 2010-197291
FIG. 5 is a schematic diagram showing a conventional compression scan circuit 200 for reducing a test time of the scan test. As sown in FIG. 5, the conventional compression scan circuit 200 includes a plurality of scan input terminals 211, scan chains 207, multiplexers 217, and a pattern deployment circuit 201. Each of the scan chains 207 is formed of scan FFs 205 arranged at a plurality of stages (for example, five stages). The pattern deployment circuit 201 is configured such that the scan input terminals 211 are connected to the scan chains 207 through the multiplexers 217. During the scan shift operation, the scan input terminals connected to the scan chains 207 are dynamically switched.
Further, the conventional compression scan circuit 200 includes scan output terminals 213, exclusive logic sum gates 219, and a pattern compression circuit 203. The pattern compression circuit 203 is configured such that the scan chains 207 are connected to the scan output terminals 213 through the exclusive logic sum gates 219.
It is noted that a majority of the scan test time corresponds to a period of time consumed for the scan shift operation. When the conventional compression scan circuit 200 shown in FIG. 5 is used for performing the scan test, it is possible to reduce the number of the stages of the scan flip-flop circuits of the scan chains 207. Accordingly, it is possible to reduce the scan shift time, thereby reducing the scan test time.
FIG. 7 is a block diagram showing a semiconductor integrated circuit subject to the conventional scan test. As shown in FIG. 7, the semiconductor integrated circuit includes a frequency division circuit 301, high speed clock flip-flop circuits 305 operating at a high speed clock, and low speed clock flip-flop circuits 307 operating at a low speed clock. When the semiconductor integrated circuit is tested in the conventional scan test, it is necessary to directly control the clock of the scan FFs from outside.
More specifically, when the semiconductor integrated circuit shown in FIG. 7 includes the frequency division circuit 301, it is difficult to perform the scan test on the semiconductor integrated circuit. Accordingly, when the scan test is performed, it is necessary to bypass the frequency division circuit 301.
Further, when it is necessary to supply clocks having different frequencies for the scan test, it is necessary to separately supply the clocks from outside. However, due to the restriction in the number of electrode pads of the semiconductor integrated circuit or the number of the terminals of the semiconductor integrated circuit, it is difficult to provide a configuration for separately supplying such clocks from outside.
On the other hand, when the high speed clock flip-flop circuits 305 are tested, the low speed clock flip-flop circuits 307 are operated without compensation. Accordingly, when the clocks having the different frequencies are supplied to one single clock terminal for performing the transition scan test, it is necessary to mask an expected value of the scan FFs.
As shown in FIG. 5, the pattern compression circuit 203 is formed of the exclusive logic sum gates 219. Accordingly, when the compression scan is applied at the same time, if the expected value of the scan FFs of the low speed clock flip-flop circuits 307 is masked, the expected value of the scan FFs of the high speed clock flip-flop circuits 305, which are arranged at the same stage as other scan chains, is masked. As a result, it is difficult to accurately detect malfunction in the compression scan test.
FIG. 6 is a schematic diagram showing the conventional compression scan circuit 200 in a compression bypass mode. As shown in FIG. 6, in the compression bypass mode, the pattern deployment circuit 201 and the pattern compression circuit 203 are bypassed for detecting a malfunction when such a malfunction is not detected in the compression scan test. In the compression bypass mode, the number of the stages of the scan FFs increases, thereby increasing the test time of the transition scan test.
In view of the problems described above, an object of the present invention is to provide a semiconductor integrated circuit capable of solving the problems of the conventional semiconductor integrated circuit. In the present invention, it is possible to accurately detect a transitional malfunction occurring in a logic circuit and the like disposed in the semiconductor integrated circuit in a short period of time.
Further objects and advantages of the invention will be apparent from the following description of the invention.